The present invention relates to formation of fin-type field effect transistors (FinFETs), and more particularly, to vertical transport FinFETs including uniform bottom spacers.
Vertical Transport FETs (VTFET) are one of the promising alternatives to standard lateral FET structures due to benefits, among others, in terms of reduced circuit footprint. In this type of structure, the current flow is perpendicular to a supporting wafer, unlike the lateral current flow in FinFETs.
However, current deposition processes such as high density plasma chemical vapor deposition (HDPCVD) for the bottom spacer fabrication are sensitive to incoming pitch walking, which can cause high inter-fin spacer height variation, and in some instances, electron dissociation and ion bombardment can result in contamination diffusion into the vertical silicon fins. Additionally, the deposited dielectric typically contains hydrogen and carbon that can result in bottom spacer loss and variation during downstream processing.